With advancements in IC scaling with smaller technology nodes, the VFET transistor architecture may be utilized for the 5 nm technology node and beyond. However, forming a self-aligned replacement metal gate in a VFET transistor is challenging since the gate structure becomes buried under top source/drain (S/D) structures. The current process flow may not be able to meet the initial VFET pitch measurements of less than 27 nm. Additionally, the current processes (e.g. chemical mechanical polishing (CMP)) for removing materials from gate structures with multiple stop materials may be inefficient and inaccurate for the VFET architecture.
Therefore, a need exists for methodology enabling production of self-aligned gate-first VFETs and the resulting devices.